1. Field
Various embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor device and a semiconductor system including the semiconductor device.
2. Description of the Related Art
As technology in the semiconductor field has advanced, a plurality of semiconductor devices have been integrated in one chip to form a semiconductor system. Each of the semiconductor devices includes a plurality of logic circuits. In general, the logic circuits need to be initialized for the semiconductor device to stably operate. The logic circuits are initialized when the semiconductor device performs an initial operation, and the logic circuits are initialized whenever the semiconductor device needs to be initialized during a normal operation.
Each of the semiconductor devices includes a one-time programmable (OTP) circuit for storing information, such as repair data. Typically, an OTP circuit includes a fuse circuit and a latch circuit, and requires a boot-up operation. The boot-up operation includes a process of reading OTP data that is stored in the fuse circuit and latching the read OTP data in the latch circuit. The boot-up operation is performed just once while the initial operation of the semiconductor device is performed.
FIG. 1 is a block diagram illustrating a conventional semiconductor system.
Referring to FIG. 1, the conventional semiconductor system includes a controller 10 and a semiconductor device 20. The controller 10 generates a power source voltage VDD and a reset control signal RESET#. The semiconductor device 20 performs reset operation based on the power source voltage VDD and the reset control signal RESET#.
Furthermore, the controller 10 controls the general operation of the semiconductor device 20. For example, the controller 10 includes a memory controller, a central processing unit (CPU) or a graphic processing unit (GPU).
The semiconductor device 20 performs the reset operation and other predetermined operations under the control of the controller 10. For example, the semiconductor device 20 includes a memory device such as a dynamic random access memory (DRAM).
FIG. 2 is a detailed diagram of the semiconductor device 20 shown in FIG. 1. FIG. 2 shows only the structure related to the reset operation.
Referring to FIG. 2, the semiconductor device 20 includes a power-up detector 21, an internal reset signal generator 23, a first internal circuit 25, a boot-up signal generator 27, and a second internal circuit 29. The power-up detector 21 generates a power-up signal PWRUP corresponding to a power-up section of the power source voltage VDD. The internal reset signal generator 23 generates an internal reset signal INIT based on the reset control signal RESET#. The first internal circuit 25 performs a reset operation based on the internal reset signal INIT. The boot-up signal generator 27 generates a boot-up signal OTP_INIT. The second internal circuit 29 performs the boot-up operation based on the boot-up signal OTP_INIT.
The power-up detector 21 detects a power-up section of the power source voltage VDD and generates the power-up signal PWRUP corresponding to the detection result. The power-up detector 21 may include a voltage distribution circuit.
The internal reset signal generator 23 generates the internal reset signal INIT by buffering the reset control signal RESET#. The internal reset signal generator 23 may include a buffer circuit.
The first internal circuit 25 performs the reset operation whenever the internal reset signal INIT is activated. The first internal circuit 25 may include a logic circuit, such as a counter circuit, and the reset operation may include a process of initializing a logic value such as a count value.
The boot-up signal generator 27 generates the boot-up signal OTP_INIT during the initial operation section, corresponding to the power-up signal PWRUP, based on the internal reset signal INIT. In other words, the boot-up signal generator 27 activates the boot-up signal OTP_INIT based on the internal reset signal INIT only in the initial operation section, and deactivates the boot-up signal OTP_INIT in the normal operation section other than the initial operation section, regardless of the internal reset signal INIT.
The second internal circuit 29 performs the boot-up operation when the boot-up signal OTP_INIT is activated. The second internal circuit 29 may include the OTP circuit. Herein, the boot-up operation includes a process of reading and latching OTP data that is programmed in the OTP circuit.
Hereafter, an operation of the general semiconductor system having the above-described structure is described with reference to FIG. 3.
FIG. 3 is a timing diagram for describing an operation of the conventional semiconductor system shown in FIG. 1.
Referring to FIGS. 1 to 3, the controller 10 supplies the power source voltage VDD to the semiconductor device 20. The controller 10 activates the reset control signal RESET# to a logic low level from a moment when it supplies the power source voltage VDD to a portion of the initial operation section R and in a normal operation section N, the controller 10 activates the reset control signal RESET# to a logic low level whenever the controller 10 requires the semiconductor device 20 to be initialized. Particularly, for a boot-up operation, the controller 10 activates the reset control signal RESET# to a logic low level of over approximately 200 μs in the initial operation section R, and then deactivates the reset control signal RESET# to a logic high level.
The semiconductor device 20 performs reset operation based on the power source voltage VDD and the reset control signal RESET#.
First, the internal reset signal generator 23 generates the internal reset signal INIT by buffering the reset control signal RESET#. The first internal circuit 25 then performs the reset operation in the initial operation section R based on the activated internal reset signal INIT.
To be specific, the reset operation includes a process of initializing an output logic value of the first internal circuit 25 into a predetermined default value. The first internal circuit 25 performs the reset operation even in the normal operation section N, based on the internal reset signal INIT, whenever the reset operation needs to be performed.
The boot-up signal generator 27 generates the boot-up signal OTP_INIT that is activated in the initial operation section R based on the power-up signal PWRUP and the internal reset signal INIT. The second internal circuit 29 then performs the boot-up operation in the initial operation section R based on the activated boot-up signal OTP_INIT. The boot-up operation may include a process of reading and latching the OTP data that is programmed in the second internal circuit 29. For reference, ‘IDLE’ denotes an idle section signal that corresponds to the initial operation section R.